Academic Projects

Processing Element (PE) design and synthesis, Independent Research

  • PIDr. Saibal Mukhopadhyay
  • TimespanMay 2017 - Present
  • CourseIndependent Research
  • Team Size1

Designed PEs for an FPGA based accelerator architecture for scientific equation solving applications. (Tools: ModelSim and Xilinx Vivado)


  • Designed and synthesized RTL for MAC and interface units; functionally verified units using testbenches via gate-level simulations
  • Developed scripts to generate Verilog files based on variable inputs


Analysis of assist techniques and variability on FinFET (10nm) and CMOS (45nm) SRAM topologies

  • PIDr. Saibal Mukhopadhyay
  • TimespanJan. 2017 - May 2017
  • CourseDigital Systems at Nanometer Nodes (ECE 8893)
  • Team Size2

Analyzed effect of assist techniques (WLOD, WLUD, NBL) and variability on cell readability and writability (6T, 8T, and 10T CMOS SRAM cells)


  • Conducted comparative analyses to study effects on CMOS and FinFET SRAM cells by performing transient simulations in HSPICE
  • Impact: Demonstrated improvements in read and write margins of 6T Bulk and FinFET cells with NBL+VDDUD+WLUD as an assist scheme


Modelling energy intensive dynamic loads in commercial buildings

  • PIDr. A. Sreedevi, Muhammad Mirash
  • TimespanJan. 2013 – Jun. 2013
  • CourseBachelor’s Thesis
  • Team Size2

Designed a simulation software for energy usage optimization of power intensive systems in commercial buildings using LabVIEW


  • Achieved 35% cost reduction of energy management systems by building a state-machine based dynamic load model


Multimodal Speech Capture System, Independent Research

  • PIDr. Maysam Ghovanloo
  • TimespanSep. 2016 – May 2017
  • CourseIndependent Research
  • Team Size1

Developed a head-mounted wearable system for rehabilitation of patients with speech disorders. Designed next generation sensor board PCB, programmed FPGAs using Verilog for signal acquisition (Technology: Mojo embedded development board; COM: SPI)


  • Improved existing SPI breakout board density by designing a 64% denser next generation PCB using KiCad
  • Developed test bench to simulate CLK and sensor inputs for system debugging (GitHub: http://tinyurl.com/y6v4qrkt)
  • Impact: Enhanced device calibration by modifying Verilog code to eliminate effect of Earth’s magnetic field on data acquisition


Out-of-order Scheduler design for a Superscalar Processor

  • PISunjae Park
  • TimespanJun. 2017
  • CourseHigh Performance Computer Architcture
  • Team Size1
  • Designed a C++ based simulator framework for a scheduler with a Register Alias table and Reservation Stations (RS)
  • Analyzed average number of instructions fired and retired per cycle (IPC), and number of issue stalls for different scheduler
  • Enabled easy configuration of parameters (RS type, entries per RS) and determined the scheduler configuration with least possible IPC


Simulation and Performance Analysis of Caches

  • PISunjae Park
  • TimespanJul. 2017
  • CourseHigh Performance Computer Architcture
  • Team Size1
  • Investigated effect of cache configurations on performance by designing a cache simulator to measure latencies and read/write miss rates
  • Determined optimal cache parameters such as cache and block size, associativity to achieve minimum Average Memory Access Time


IEEE 802.11 a/g WLAN Direct down conversion RX design

  • PIDr. Hua Wang
  • TimespanNov. 2016 - Dec. 2016
  • CourseWireless IC Design
  • Team Size2
  • Designed a wideband direct down conversion RX for broadband Wi-Fi applications using 130nm technology in Advanced Design Systems
  • Improved the initial design to achieve an FOM of 6300 (20X higher than design requirement); BW: 0.8-6 GHz